Imaging arrays and, in particular, large area amorphous silicon imaging arrays are adversely impacted by parasitic capacitances along the data and gate lines of the device. Currently, the inter-layer dielectric, which separates the data and gate lines, on digital imaging arrays is deposited by using a chemical vapor deposition (CVD) process. The topography of this layer over the array is highly varied/conformal, or non-planar. This non-planarity/conformality lends itself to thinner areas at data to gate crossovers leading to higher parasitic capacitances and degraded array performance. This non-planarity also contributes to lower reliability of the arrays by allowing moisture to penetrate through a seam that is propagated through each CVD process.
Referring now to FIG. 23, a prior art imaging array is shown including a glass substrate 302, a chrome metallization layer 304, a thin film transistor (TFT) including an island 306 and a gate 308, an amorphous silicon photodiode including an n+ layer 310, an intrinsic layer 312, a p+ layer 314, and an Indium Titanium Oxide (ITO) layer 316, and a conformal insulating layer 318. The prior art imaging array includes a first metalized via 322 for contacting the chrome metallization layer 304 and a second metalized via 324 for contacting the ITO layer 316 of the photodiode. The first and second vias 322 and 324, as well as other patterned metal areas on the surface of the conformal insulating layer 318 comprise a trilayer metallization including a Titanium-Tungsten (TiW) layer 326, an aluminum layer 328, and a Titanium-Tungsten (TiW) layer 330. The entire imaging array is passivated with a conformal passivation layer 332. The problem with the imaging array shown in FIG. 23 is that there is an ingress path 334 for moisture, which can damage the photodiode and decrease overall reliability.
What is desired is an amorphous silicon imaging array having improved reliability and addresses these problems in the prior art arrays.